Hearing Aid Abstract
Hearing Aid Claims 1. A system for processing digital signals of a hearing aid device, the system comprising: an audio input signal representative of a sound level; a digital filter for processing the audio input signal, the digital filter including coefficient multipliers to provide selective weighting of discrete components derived from the input signal at stages of the digital filter, the coefficient multipliers supporting coefficient multiplication via bitshifting to produce selected weights of corresponding discrete components at stages of the digital filter; and an output of the digital filter, the output depending at least in part on the coefficient multiplication of components at corresponding stages of the digital filter, at least one stage of the digital filter including a multiplier circuit, a selected multiplicand input of the multiplier circuit controlling a corresponding frequency response such that the digital filter provides a frequency response about that provided by transfer function H(z)=z.sup.2 +.lambda.(2.sup..gamma. z.sup.2 +G(z).sup.S), where G(z)=(0.5+0.5 z.sup.1 +0.125z.sup.2) (1+0.25z.sup.1) (1z.sup.1), and where .gamma. controls the magnitude of the frequency response at a higher frequency range, and .gamma. controls the magnitude of the frequency response at lower frequency range, and S selects a slope of the frequency response between the high and low frequency ranges. 2. A method for processing digital signals of a hearing aid device, the method comprising: receiving an audio input signal representative of a sound level; processing the audio input signal using a digital filter, the digital filter including coefficient multipliers to provide selective weighting of discrete components derived from the input signal at stages of the digital filter; supporting coefficient multiplication via bitshifting to produce selected weights of corresponding discrete components at stages of the digital filter; and producing an output of the digital filter, the output depending at least in part on the coefficient multiplication of the discrete components at corresponding stages of the digital filter, the digital filter providing a frequency response about that provided by transfer function H(z)=(1+.alpha..beta.) U(z)(1+.alpha.) V(z) , where U(z)=(0.5+0.5 z.sup.2), V(z)=(0.50.5 z.sup.2).sup.n, and where a controls the magnitude of the frequency response at a higher frequency range, and .beta. controls the magnitude of the frequency response at lower frequency range, and n selects a slope of the frequency response between the high and low frequency ranges. 3. A method for processing digital signals of a hearing aid device, the method comprising: receiving an audio input signal representative of a sound level; processing the audio input signal using a digital filter, the digital filter including coefficient multipliers to provide selective weighting of discrete components derived from the input signal at stages of the digital filter; supporting coefficient multiplication via bitshifting to produce selected weights of corresponding discrete components at stages of the digital filter; and producing an output of the digital filter, the output depending at least in part on the coefficient multiplication of the discrete components at corresponding stages of the digital filter, the digital filter providing a frequency response about that provided by transfer function H(z)=z.sup.2 +.lambda.(2.sup..gamma. z.sup.2 +G(Z).sup.S), where G(z)=(0.5+0.5 z.sup.1 +0.125 z.sup.2) (1+0.25z.sup.1) (1z.sup.1), and where .lambda. controls the magnitude of the frequency response at a higher frequency range, and .gamma. controls the magnitude of the frequency response at lower frequency range, and S selects a slope of the frequency response between the high and low frequency ranges. Patent Information Search Body
Hearing Aid Description This invention generally relates to hearing aid digital filters, and more particularly, is directed to a hearing aid digital filter with reduced power consumption and dissipation. Digital Signal Processors (DSP), which are known to be used in hearing aid systems hitherto, have emphasized speed and performance, and have been traditionally of a design which requires significant amounts of power. Significant power consumption in DSPs is basically because of the components and the manner of interconnection thereof. The present invention is directed to a DSP for a hearing aid where the power consumption is minimized with consequent advantages of economy and size without sacrificing performance. In a conventional hearing aid, a microphone converts incident sound waves into an analog electrical signal which is then processed to filter out unwanted noise etc., amplified, and coupled to a receiver or speaker which converts the electrical signal back to sound waves. The electrical signal processor may be an analog processor which operates directly upon an analog electrical signal. Alternatively, the analog signal may be converted to a digital signal and processed by a digital signal processor (DSP). Most hearing aids nowadays use analog signal processing. Signal processing schemes include frequencyindependent linear amplification, frequencycompensated linear amplification (typically boosting the high frequencies), frequencyindependent automatic gain control (AGC) systems, and finally signal level dependent, frequency compensated systems. This final class of hearing aids includes signal processing algorithms that the hearing aid community labels 2channel systems, 3channel systems, and multichannel systems. These systems split the audio frequency band up into two or more sections and can control the gain of each section independently from one another. The KAmps.RTM. circuits from Etymotic Research and the DynamEQI.RTM. circuits from Gennum Corporation are examples of traditional 2channel systems. The DynamEQI.RTM. has two amplifier sections, one processes the low frequencies and the other processes the high frequencies. This, in the traditional sense, is a twochannel system. The KAmp contains only one amplifier to shape the frequency response as a function of input level. Both of these circuits implement a first order analog filter although in different ways. Therefore, one must be careful when using the term 2channel system. A description of the complexfrequency transfer function (written in the sdomain) is a more appropriate way to describe analog filters. The accuracy and repeatability of analog filters depend on the tolerances of physical components (e.g., resistors and capacitors). These components have initial tolerances, which vary with temperature, and can also vary with humidity, voltage, and age. It can be quite a challenge to design an analog filter to meet its intended requirements when operating over a range of environmental conditions. Digital filters on the other hand are implemented with digital electronics that manipulate numbers. Digital filters are described by algorithms, and are represented mathematically in the zdomain. The repeatability of the digital filter from circuit to circuit depends only on the accuracy of the sampling frequency. This sampling frequency is usually derived from a crystalcontrolled oscillator with a typical accuracy of 0.01 percent. The precision of the oscillator frequency is much better than the typical 1%, 5%, and 10% tolerances of resistors and capacitors used in analog filters. The accuracy, distortion, and noise characteristics of the digital filter depend on the precision with which the signal and filter coefficients are represented. There exist several prior art US patents which relate to hearing aid technology. U.S. Pat. No. 4,803,732, entitled Hearing Aid Amplification Method and Apparatus, to Dillon, recognizes different audiofrequency bands and handles them independently. The different frequency bands are independently amplified to match the needs and loss pattern of hearing of the user. Prior to amplification, the microphone signal is passed through an optional filter. Thus, signal discrimination for the user is increased. U.S. Pat. No. 4,791,672 to Nunley et al is directed to a hearing aid which includes a wearable, programmable digital signal processor for processing digital samples of analog signals in real time. A hearing aid program stored in a signal processor is continuously executed, introducing noise suppression. Prior art is replete with US patents which are, in one way or the other, directed to noise suppression in different degrees, using different arrangements or techniques. Examples of such prior art include US patents: U.S. Pat. No. 5,794,187 to Franklin, et al., U.S. Pat. No. 5,651,071 to Lindemann, et al., U.S. Pat. No. 4,185,168 to Graupe, et al., U.S. Pat. No. 5,306,560 to Arcos, et al., 5,259,033 to Goodings, et al, and U.S. Pat. No. 5,412,735 to Engebretson, et al. Generally, the aforesaid patents are directed to achieving clarity of hearing or enhanced hearing for the user without any reference to the power consumed in the amplifier and associated circuitry. A general method for describing the action of a digital filter on a digital signal is the Ztransform method. ZTransform A brief discussion of the Ztransform at this juncture is believed to assist in providing a better understanding of the invention. Let X (k) be a digital signal that is zero for k<0. Its ztransform, denoted by X*(z), is defined to be the function of z: ##EQU1## Because of the shiftmultiplication property which is being aimed for, z will have the same interpretation as does a phasor approach. That is, when z is on the unit circle in the complex zplane, its angle is interpreted as a frequency variable. But the question is not how is z interpreted, but rather how is z defined. The answer is: z is an independent complex variable. It has much the same status as k, the sample number. A signal is defined to be a function of k, while its ztransform is defined to be a function of z. Thus, z is the domain of the ztransform of a signal. In fact, the ztransform can be looked at as a transformation from the time domain to the frequency domain. The following symbolism may be used for the ztransform: ##EQU2## The symbol over the arrow indicates the name of the transformation. It is noted at this point that a digital filter can be thought of as a transformation in the same way as the ztransform. For example, if X is the input filter to a filter H. and Y is the output, a relationship can be expressed as: ##EQU3## Thus, a filter is a transformation that converts one function of k to another function of k, while the ztransform converts one function of k to another function of z. Ztransforms have certain properties which make it possible to represent moving average filters and other linear timeinvariant filters by multiplication, similar to an approach which deals with phasors. For a onesided digital input signal, the ztransform of the output signal can be obtained by multiplying the ztransform of the input signal by the transfer function H(z). Ztransforms have a property which enables easy and free movement from the time domain to the frequency domain. Filtering in the time domain can be looked at as corresponding to multiplication in the ztransform domain. A more complete understanding of the above can be had from An Introduction to Discrete Systems by Kenneth Steglitz, Princeton University, John Wiley & Sons, Inc. 1974. Filter Coefficients: A digital filter is characterized by a set of real numbers, namely its coefficients. Altering these numbers will alter the characteristics of the filter. To assess the effect of any change in the value of a coefficient on a given filter characteristic, say the frequency response, one may differentiate .vertline.H(e.sup.jwt).vertline. with respect to that coefficient and use of the value of the derivative as an indication of the sensitivity of the frequency response to changes in the particular coefficient. A more detailed analysis of the choice of coefficients on the filter characteristic can be found in chapter 2, Design of Digital Filters, p. 45 of Digital Signal Processing by Abraham Peled and Bede Liu. A digital filter H(f) may be expressed as a Fourier series: ##EQU4## analysis of phase shifts of a symmetric Finite Impulse Response (FIR) as influenced by the choice of the filter coefficient h(n) is given in Digital Signal Processing in VLSI by R. Higgins, pp. 182191, Prentice Hall, Englewood Cliffs, N.J., 1990. The choice of the filter coefficients h(n) which are the ztransform of H(z) in the frequency domain and the time domain significantly influence the filter characteristics. A detailed analysis of the design considerations in designing digital filters, especially from the point of view of the choice of multiplier coefficients can be found in the publication IIR Digital Filter Design using Minimum Adder Multiplier Blocks by A. G. Dempster and M. D. Macleod in IEEE Transactions on Circuits and SystemsIT Analog and Digital Signal Processing, vol. 45, no. 6, pp. 761763, June 1998. The publication describes details of how specific values chosen for the multiplier coefficients influence the performance of the filter. The publication also explains how the coefficient word length (i.e., the number of bits) required for a digital filter is related to the coefficient sensitivities, and states that different filter structures can require widely different word lengths to meet a required filter specification. A reference is made in the publication to the high cost of coefficient multipliers. General purpose digital signal processors are available. Motorola, Texas Instruments, and Analog Devices are three examples of manufacturers of these devices. The goal of these processors is to be fast and flexible so that a large number of different types of signal processing can be implemented. The penalty to be paid for this speed and flexibility is power and the size of the integrated circuit. Also, these devices have traditionally operated on a +5 volt supply. The trend is towards lower operating voltages and presently there are several devices that operate on +3.3 volts. The power source for a hearing aid is generally a zincair battery that provides +1.3 volts. The endoflife voltage for the zincair cells is usually specified as +0.9 volts, +1.0 volts, or +1.1 volts depending on the manufacturer. Hearing aid integrated circuits are typically specified to operate within specifications down to +1.1 volts. To use digital signal processing in a hearing aid, then requires the DSP chip to operate down to at least +1.1 volts, and preferably +1.0 volts. To maximize battery life, the current drain needs to be very low. For example, in order for a 675cell, rated at 550 mAh to last for 31 days continuously (24 hours per day), the average current drain on the battery must be no greater than 740 .mu.A (0.74 mA). This current includes the current for the microphone, the analogtodigital converter (ADC), digital signal processing circuitry (DSP), digitaltoanalog converter (DAC), audio power amplifier, and receiver (speaker). To conserve battery current, the audio power amplifier may be implemented as a classD amplifier. Knowles Electronics offers several receivers with builtin classD amplifiers. A Knowles electret microphone consumes an average current of about 20 .mu.A, while the classD amplifier and receiver consume an average current of about 550 .mu.A depending on signal level. This leaves about 170 .mu.A of current available for the remainder of the electronics (ADC, DSP, and DAC). Another attempt to conserve power is to eliminate the conversion from digital back to analog, and rather use a digitaltodigital converter (as in the Widex Sensot.RTM. digital hearing aid, for example). This digitaltodigital converter (DDC) drives the receiver in a classD scheme, but uses the digital words to directly control the dutycycle of the signal applied to the receiver. General purpose DSP chips provide an architecture that is flexible. A generic DSP device consists of various functional blocks including accumulators, adder/subtractors, multipliers, registers, data memory, and program memory. These functional blocks are multiplexed to minimize the number of blocks needed. When two numbers need to be multiplied, the numbers are fetched from memory and latched into the input registers of the multiplier. The output of the multiplier contains the result, which is then stored in another register or in memory. SUMMARY OF THE INVENTION The present invention uses a digital filter and achieves minimized power consumption with the attendant advantages of low cost and smallness in size without significantly sacrificing performance. It is the object of this invention to provide a hearing aid using a digital filter where power consumption is minimized, thus resulting in size advantage and cost economy. In one form, the invention resides in a digital signal processor for a hearing aid of the type using a signal level dependent frequency compensated system within a digital filter, comprising a general purpose multiplier to control frequency response as a function of a predetermined e.g., input signal level, and an infinite impulse response digital filter (IIR) used as a digital filter, said digital filter having filter coefficients which are generically related to 2.sup.n, n being an integer, thereby minimizing power consumption in the digital signal processor. In a second form, the invention provides a digital signal processor for a hearing aid of the type using a signal level dependent frequency compensated system within a digital filter, comprising a general purpose multiplier to control frequency response as a function of a predetermined parameter, e.g., input signal level, and a nonrecursive finite impulse response digital filter used as a digital filter, said digital filter having filter coefficients which are generically related to 2.sup.n, n being an integer, thereby minimizing power consumption in the digital signal processor. This invention concentrates on minimizing the power consumption of the DSP algorithm portion of a digital hearing aid by using signal processing algorithms that can be implemented in a minimum amount of dedicated circuitry. This circuitry would normally be contained within an integrated circuit. In a first preferred embodiment of the invention, circuitry is minimized in three ways: First, only one general purpose multiplier is used to change the frequency response as a function of signal level, second, the filter coefficients are values represented by 2 raised to the nth power, and third, a nonrecursive (finite impulse response) filter is used. Only one general purpose multiplier: In the present invention, a single general purpose multiplier is used, and the coefficients are fixed and limited to figures relating to powers of 2; the coefficient multipliers become shifters if the coefficients are values which can be represented as 2.sup.n. In this invention, a coefficient multiplier functions as a shifter rather than a multiplier. The shifter function does not need consumption of additional amounts of power expenditure, unlike in the case of a coefficient multiplier. Since general purpose multipliers require more circuitry than other functional blocks such as adders, it is desirable to minimize the number of such multipliers. If many general purpose multipliers are needed, a multiplexed multiplier, such as that used in DSP devices, makes more sense. However, if only one general purpose multiplier is needed, a dedicated multiplier may be use&, and the multiplexing circuitry is eliminated. Accordingly, in this invention only one general purpose multiplier is employed. Filter coefficients with values of powers of two: In digital filters, as aforesaid, the filter coefficients are selected to achieve the desired filter characteristics. These coefficients are multiplied with timedelayed data values. Normally, this is performed with a general purpose multiplier. By constraining the filter coefficients to powers of 2, the multiplier becomes a simple shifter. lifting hardware is simpler to implement than multipliers. However, since this invention provides only a dedicated signal processing function, the coefficients are fixed and the multiplier is implemented merely by routing the correct bits to their destinations. It will be shown below that filters with the needed characteristics can be achieved with coefficients constrained to powers of two. In another implementation of the invention, the filter coefficients are not, per se, powers of 2, but rather the sum of two numbers, both of which are powers of two. To implement the multiplication needed, the data signal is shifted, then added (or subtracted) from the unshifted signal. Only a single adder is required to achieve the multiplication needed. Multiplications by powers of 2 are implemented by the circuit connections and do not require any hardware, and hence do not use any power from the battery. Use of nonrecursive filter: Nonrecursive or finite impulseresponse (FIR) filters have several advantages over recursive or infinite impulseresponse (IIR) filters. FIR filters do not have poles and hence are unconditionally stable. The IIR filters do have poles and therefore can become unstable and oscillate. FIR filters do not accumulate errors since only a finite number of past input samples are used. The IIR filters on the other hand, use a finite number of past input samples and past output samples. Therefore, errors can accumulate, and limitcycle oscillations may become a problem. Whereas 16bits may be adequate for FIR filters, 24bits may be needed in IIR filters to handle truncation and roundoff errors. Although the description for the preferred embodiment of this invention uses FIR filters, the invention may also be implemented with IIR filters. BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. FIG. 1 is a generic block diagram for the digital signal processor of the invention. FIG. 2 is a block diagram of a first order filter with no low frequency boost. FIG. 3 is a plot of frequency response for a filter of FIG. 2 at various .lambda.s. FIG. 4 is a block diagram of a first order filter with low frequency boost. FIG. 5 is a plot of frequency response for the filter of FIG. 4 at various .lambda.s. FIG. 6 is a block diagram of a first preferred embodiment of the invention. FIG. 7 is a set of frequency response curves in which the slope or s parameter is varied for the embodiment of FIG. 6. FIG. 8 is a plot of frequency response curves as in FIG. 7 where s=1, .gamma.=16 and .lambda. ranges from 016. FIG. 9 is a plot as in FIG. 8 where y=3. FIG. 10 is a plot as in FIG. 8 where s=2, .gamma.=16 and .lambda.=0 to 16. FIG. 11 is a plot as in FIG. 8 where s=2, .gamma.=4 and .lambda.=0 to 16. FIG. 12 is a plot as in FIG. 8 where s=2, .gamma.=3and .lambda.=0 to 16. FIG. 13 is a plot as in FIG. 8 where s=2, .gamma.=2 and .lambda.=0 to 16. FIG. 14 is a set of frequency response curves for s=3, .gamma.=16 and .lambda.=0 to 16. FIG. 15 is a set of frequency response curves for s=3, .gamma.=3 and .lambda.=0 to 16. FIG. 16 is a block diagram of a most preferred embodiment of the invention. FIG. 17 is a plot of a family of frequency response curves for .alpha.=17, .beta.=0 and .eta.=1. FIG. 18 is a plot of a family of frequency response curves for .eta.=1, .beta.=0 and .alpha. ranging from 0 to 16. FIG. 19 is a plot of a family of frequency response curves for .beta.=0.125 and .alpha. ranging from 0 to 16. FIG. 20 is a plot of a family of frequency response curves for .eta.=2, .beta.=0 and .alpha. ranging from 0 to 16. FIG. 21 is a plot of a family of frequency response curves for .eta.=2, .beta.=0.125 and .alpha. ranging from 0 to 16. FIG. 22 is a plot of a family of frequency response curves for .eta.=3, .beta.=0 and .alpha. ranging from 0 to 16. FIG. 23 is a plot of a family of frequency response curves for .eta.=3, .beta.=0.125 and .alpha. ranging from 0 to 16. DETAILED DESCRIPTION OF THE INVENTION While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. In accordance with the invention, a generic digital signal processing algorithm that is suitable for use in lowvoltage, lowpower hearing aid applications is described herein. The preferred embodiment may be structured, depending on the desired signal processing. Several embodiments of the invention will be described and will illustrate the inherent features of the invention. Digital signal processing algorithm: Within the constraints outlined above, this invention provides the generic digital signal processing algorithm described by the following system function equation in the zdomain: Transfer Function H(z)=.sigma..multidot.z.sup..delta. +.lambda..multidot.[2.sup..gamma..multidot..sigma..multidot.z.sup. .delta. +G(z)] (1) where where z.sup.1 is a unit delay, a.sub.0 . . . a.sub.n are the filter coefficients, and G(z) is a FIR filter. The parameter .sigma. takes on a constant value of either +1 or 1 depending on the actual filter being implemented, and .delta. defines an output tap of the delay line. The parameter .gamma. defines the low frequency response, and .lambda. is a parameter that controls the signal leveldependent frequency response. In the hearing aid application, .lambda. will be controlled by the level of one of several signals such as: (1) the input signal, (2) the output signal, (3) the signal at the input to the .lambda.multiplier, or the signal at the output of the .lambda.multiplier. FIG. 1 is a generic signal processing block diagram of the invention. It shows a circuit schematic of a digital filter where x(i) shows the input and y(i) shows the signal after passing through the filter. Z.sup.1 is a unit delay, and a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n are the filter coefficients which are used to multiply with a corresponding one unit delay, two unit delay, etc., up to a n unit delay Z.sup.n as per equation 2. The schematic shows .lambda., which is a parameter that controls the signal leveldependent frequency response. As aforesaid, .lambda. can be controlled by the level of one of several signals such as the input signal, or the signal to the input to the .lambda. multiplier or the signal at the output of the .lambda. multiplier. .delta. shows the different selectable taps to obtain different levels of delay. The parameters .sigma., as aforesaid in the context of equation 1, takes on a constant value of either +1 or 1, depending on the actual filter being implemented. First order filter with no lowfrequency gain: FIG. 2 shows the block diagram of a first order implementation of the invention. There is no lowfrequency gain (.gamma.=.infin.). With .lambda.=0, the frequency response is flat. As .lambda. is increased, the high frequencies are boosted. The maximum rate of high frequency boost is 6 dB per octave. FIG. 3 shows the frequency responses for .lambda. ranging from 0 to 32. The sampling rate is 40,000 samples per second. First order filter with lowfrequency gain: FIG. 4 shows the block diagram of a first order implementation of the invention. The lowfrequency gain is controlled by the .gamma. parameter. With .lambda.=0, the frequency response is flat. As .lambda. is increased, both high and low frequencies are boosted. However, the low frequencies are boosted less than the high frequencies. The amount of low frequency boost is affected by both .gamma. and .lambda. parameters. The maximum rate of high frequency boost is 6 dB per octave. FIG. 5 shows the frequency responses for .gamma.=4 and .lambda. ranging from 0 to 32. The sampling rate is 40,000 samples per second. In hearing aid applications, filters with 6, 12, and 18 dB per octave slopes are often needed. To achieve this, the filter configuration of FIG. 6 provides an easily selectable slope, uses only one generic multiplier, and has filter coefficients of powers of two. With such data, signal processing can be expressed as follows: where .lambda.is a leveldependent gain parameter, .gamma.controls the amount of low frequency amplification, and s=1, 2, or 3 and selects a slope of 6, 12, or 18 dB per octave. It should be noted that the digital filter G(z) is implemented using filter coefficients that are only powers of two. However, G(z) may be rearranged as follows: Equations 4 and 5 are equivalent, even though the coefficients in equation 5 are not all powers of two. This does not violate the spirit of the invention, since the filter was implemented with coefficients of powers of two (equation 4). The filter G(z) was also selected to have a peak gain of close to 1 (ideally it would be one), such that the peak gain of G(z) raised to the power s (equation 3), also has a peak gain of about one. A user programmable hearing aid can then be implemented with selectable slopes of 6, 12, or 18 dB/oct, while maintaining the same maximum gain. An estimate of the power dissipation for this preferred embodiment will now be made based on the block diagram of FIG. 6. First an estimate of gate count is made for each functional element: delay register, adder, and multiplier. It is assumed that the width of the data is 20 bits. Gate counts are made based on the gate counts of similar CD4000 series CMOS logic parts as follows: Delay registerbased on a CD4174 hex type D flipflop. The CD4174 has an equivalent gate count of 43.5 gates, or 7.25 gates per bit. A 20bit register then has 145 gates. Adderbased on a CD4008 4bit full adder. The CD4008 has an equivalent gate count of 40 gates. Therefore a 20bit adder has 200 gates. Multiplierbased on an array multiplier [A. Peled and B. Liu, Digital Signal Processing, Theory, Design, and Implementation, John Wiley & Sons Inc., New York, 1976; R. Higgins, Digital Signal Processing in VLSI, Prentice Hall, Englewood Cliffs, N.J., 1990], the number of equivalent gates for a n.times.m multiplier is estimated by ##EQU5## where n and m are the number of bits for each of the multiplicands, n>m, and m.gtoreq.2. Then, from equation (6), a 20bit by 20bit multiplier requires 4020 equivalent gates. The rough orderofmagnitude gate count of the digital filter shown in FIG. 6 can now be made as follows: Element Gates Quantity Total gates Delay register 145 12 1740 Adder 200 14 2800 Multiplier 4020 1 4020 8560 To estimate the power dissipation, an estimate of the dissipation per gate is needed. Lowvoltage, low power CMOS processes have achieved power dissipation figures of 0.05 .mu.W/MHz/gate for 0.5V MT CMOS [T. Douseki, S. Shigematsu, J. Yamada, M. Harada, H. Inokawa, and T. Tsuchia, A 0.5VMTCMOS/SIMOX Logic Gate, IEEE J. SolidState Circuits, vol. 32, no. 10, pp. 16041609, 1997]. Then for 1.3 volt operation, 0.34 .mu.W/MHz/gate may be assumed. For the digital filter operating at a sampling rate of 40 kHz, the total power dissipation is given by At a voltage of +1.3 volts, the battery current would be only 90 .mu.A. Additional power savings can be obtained by using a more efficient multiplier, or using a lower sampling rate. For example, at a sampling rate of 32 kHz, the battery current would be 72 .mu.A instead of 90 .mu.A. If a 20.times.10 multiplier is used (20bit data and 10bit control signal), a savings of 2100 equivalent gates is achieved. At 1.3 V and a 40 kHz sampling rate, this results in a savings of 29 .mu.W (22 .mu.A), or 24 percent. Using a 20.times.10 multiplier, the currents become 68 .mu.A (at 40 kHz sampling) and 54 .mu.A (at 32 kHz sampling). As demonstrated, this filter configuration consumes very low power levels from the battery. Frequency response of preferred embodiment: The frequency response of the preferred digital filter described by equation (3) depends on parameters .lambda., .gamma., and s. The .lambda. parameter controls the gain of the filter. The .gamma. parameter controls the lowfrequency gain relative to the highfrequency gain. Finally, the s parameter selects a maximum nominal slope of 6, 12, or 18 dB/oct. FIGS. 715 show typical frequency responses that can be achieved by varying the different parameters. FIG. 7 shows the effect of selecting different slopes. A family of frequency response curves for .lambda.=16, .gamma.=16, and s=1, 2, and 3 are shown. The peak gain is set by .lambda. and is about 24 dB regardless of the selected slope. The low frequency gain is 0 dB (i.e., unity gain) and is set by setting .gamma. to about 16 or greater. The gain above 7.5 kHz is reduced to minimize highfrequency noise for hearing aid applications. FIG. 8 shows a family of frequency response curves for s=1, .gamma.=16, and .lambda. ranging from 0 to 16. For highlevel signals (i.e., loud sounds), .lambda. would be driven towards zero and the frequency response becomes flat. For lowlevel signals (i.e., soft sounds), .lambda. increases towards 16 and the high frequency gain also increases. Since .gamma. is set to 16, there is no lowfrequency amplification. FIG. 9 shows the same filter used for FIG. 8 except that .gamma.=3. Now as .lambda. increases towards 16, the gain at low frequencies also increases, although not as much as the gain at highfrequencies. FIGS. 1013 show frequency response curves for a filter with s=2 and .lambda. ranging from 0 to 16. The different figures demonstrate the effect of varying y. In FIG. 10, .gamma.=16, and there is no lowfrequency gain. In FIG. 11, .gamma.=4. In FIG. 12, .gamma.=3. Finally in FIG. 13, .gamma.=2. FIGS. 1113 have lowfrequency gain with the maximum lowfrequency gain increasing in 6 dB steps as y goes from 4, to 3, to 2. FIGS. 14 and 15 show frequency response curves for a filter with s=3 and .lambda. ranging from 0 to 16. In FIG. 14, .gamma.=16, while in FIG. 15, .gamma.=3. Other filter configurations are possible within the scope of this invention. These filters may be more or less complex than the preferred embodiment disclosed herein. This disclosure teaches the techniques used to minimize the circuitry needed to implement digital filters, and hence minimize the power dissipation and battery current. FIG. 16 shows the block diagram of another preferred embodiment of the invention which uses less circuitry than the previous preferred embodiment, and therefore is more preferred. The signal processing utilized in FIG. 16 can be described in the zdomain as follows: where the parameters used are previously defined in connection with equation 1. An estimate of the power dissipation for this preferred embodiment will now be made based on the circuit of FIG. 16. First an estimate of gate count is made for each functional element: delay register, adder, and multiplier. As before, based on an assumption that the width of the data is 20 bits, the gate counts are based on the gate counts of similar CD4000 series CMOS logic parts as follows: Delay registerbased on a CD4174 hex type D flipflop. The CD4174 has an equivalent gate count of 43.5 gates, or 7.25 gates per bit. A 20bit register then has 145 gates. Adderbased on a CD4008 4bit full adder. The CD4008 has an equivalent gate count of 40 gates. Therefore a 20bit adder has 200 gates. Multiplierbased on an array multiplier [A. Peled and B. Liu, Digital Signal Processing, Theory, Design, and Implementation, John Wiley & Sons Inc., New York, 1976; R. Higgins, Digital Signal Processing in VLSI, Prentice Hall, Englewood Cliffs, N.J., 1990], the number of equivalent gates for a n.times.m multiplier is estimated by ##EQU6## where n and m are the number of bits for each of the multiplicands, n>m, and m.gtoreq.2. Then, from equation (4), a 20bit by 20bit multiplier requires 4020 equivalent gates. Element Gates Quantity Total gates in FIG. 16 Embodiment Delay register 145 6 870 Adder 200 7 1400 Multiplier 4020 1 4020 6290 To estimate the power dissipation, an estimate of the dissipation per gate is needed. Lowvoltage, low power CMOS processes have achieved power dissipation figures of 0.05.mu.W/MHz/gate for 0.5V MTCMOS [T. Douseki, S. Shigematsu, J. Yamada, M. Harada, H. Inokawa, and T. Tsuchia, A 0.5V MTCMOS/SIMOX Logic Gate, IEEE J. SolidState Circuits, vol. 32, no. 10, pp. 16041609, 1997]. Then for 1.3 volt operation, 0.34 .mu.W/MHz/gate may be assumed. For the digital filter operating at a sampling rate of 32 kHz, the total power dissipation is given by At a voltage of +1.3 volts, the battery current would be only 53 .mu.A. This compares to a gate count of 8560 and a battery current of 72 .mu.A for the FIG. 6 embodiment previously disclosed. Additional power savings can be obtained by using a 20.times.10 multiplier (20bit data and 10bit control signal) instead of the 20.times.20 multiplier. This would save about 2100 equivalent gates. From equation (11), the power dissipation is calculated and is 45.6 .mu.W. At 1.3 V this would be a battery current of only 35 .mu.A. As demonstrated, this filter configuration consumes very low power levels from the battery. Frequency response of preferred embodiment of FIG. 16: The frequency response of the preferred digital filter described by equation (8) through (10) depends on parameters .alpha., .beta., and n. The .alpha. parameter controls the highfrequency gain of the filter. The .beta. parameter controls the lowfrequency gain relative to the highfrequency gain. Finally, the n parameter selects a maximum nominal slope of 6, 12, or 18 dB/oct. FIGS. 1723 show typical frequency responses that can be achieved by varying the different parameters. FIG. 17 shows the effect of selecting different slopes. A family of frequency response curves for .alpha.=17, .beta.=0, and n=1, is shown. The peak gain is set by .alpha.=17 and is about 24 dB regardless of the selected slope. The low frequency gain is 0 dB (i.e., unity gain) and is set by setting .beta. to zero. Above 8 kHz the gain is decreases from the peak gain of 25 dB to 0 dB at 16 kHz to minimize highfrequency noise for hearing aid applications. FIG. 18 shows a family of frequency response curves for n=1, .beta.=0, and .alpha. ranging from 0 to 16. For highlevel signals (i.e., loud sounds), .alpha. would be driven towards zero and the frequency response becomes flat. For lowlevel signals (i.e., soft sounds), .alpha. increases towards 16 and the high frequency gain also increases. Since .beta. is set to 0, there is no lowfrequency amplification. FIG. 19 shows the same filter used for FIG. 18 except .beta.=0.125. Now as .alpha. increases towards 16, the gain at low frequencies also increases, although not as much as the gain at highfrequencies. FIGS. 2023 show the frequency response for n=2 and 3 with .beta.=0.125, as .alpha. ranges from 0 to 16. Equivalents While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
